1. Field of the Invention
This invention relates to a "thermally enhanced quad flat non-lead package" of semiconductor., and more particularly to a "thermally enhanced quad flat non-lead package of semiconductor" for improving the heat-dissipating effect of the package.
2. Description of Related Art
In the information explosion of the world nowadays, the integrated circuit has become indispensable in our daily life, regardless of our daily life in food, clothing, lodging, transportation, education, and entertainment, the product assembled by various integrated circuit devices can be found everywhere. Following the evolution of the electronic technology, more sophisticate electronic products with user friendly and complicated functions are continuously progressing and changing. Nevertheless, in order to provide an ongoing convenience and comfortable usage, all the products are heading for the design trend of "Light, Thin, Short, and Small". In additions, the fabrication process of semiconductor has stepped into the mass production era of 0.18 .mu.m integrated circuit, and semiconductor products with even higher integration have become at hands easily. As for packaging technology of the back stage, there are many successful cases on the development of precise package structure, i.e. chip scale package (CSP), wafer level package, and Multi-Chip Module (MCM) etc. However, in the respect of the assembly technology of devices, there is also a multi-level printed circuit board (PCB) with even higher density which make the integrated circuit (IC) package even closely and densely dispose on the printed circuit board.
FIG. 1 is a cross-sectional view of a Quad Flat Non-Lead package of a semiconductor according to the prior art and FIG. 2 is a bottom view corresponding to FIG. 1 according to the prior art. As shown in FIG. 1 and FIG. 2, the structure of the Quad Flat Non-Lead package which has disclosed in the U.S. Pat. No. 5,942.794 (Matsushita, 1999) is constructed on a lead frame and is having a die pad 100 surrounded by a plurality of leads 102. The chip 104 includes an active surface 106 and a back surface 108. And a plurality of bonding pads 110 for external connections of the chip 104 is set up on the active surface 106. The chip 104 has its back surface 108 bonded to the die pad 100 by the use of an adhesive 112 while the bonding pads 110 are electrically connected to the top surface 118a of the leads 102 by the use of bonding wires 114. What is more, the molding compound 116 normally encapsulates the whole chip 104, die pad 100, bonding wire 114, and the top surface 118a of the lead 102 while exposes the bottom surface 118b and the side surface 118c of the leads 102. The leads 102 are used for external connections of the whole package structure 120.
In the conventional structure of the Quad Flat Non-Lead package, the die pad 100 is upward offset in order to make the chip 104 and leads 102 positioned at different level of surfaces. An object of the upward offset of the die pad 100 is that the package can be applied in a relatively large chip in order to increase the packaging density, while the other object is to increase the bondability between the molding compound 116 and the lead frame. However, because of the demand for diminishing the thickness of the package, this conventional package structure is apt to expose the bonding wire 114 while encapsulating, thereby, the yield of the product become lower. Additionally, as the operating speed of the device of the integrated circuit becomes faster and faster nowadays. the heat generated increases accordingly, and since the conventional package structure is unable to provide a better way of heat dissipation, the performance of the electronic device will be affected.